SH7263 Datasheet, PDF (1000/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-TL1)
19.3.5 Timer Registers
The Timer is 16 bits and supports several source clocks. A pre-scale counter can be used to reduce
the speed of the clock. It also supports three Compare Match Registers (TCMR2, TCMR1,
TCMR0). The address map is as follows.
Important: These registers can only be accessed in Word size (16-bit).
Description
Address
Timer Trigger Control Register 0 080
Cycle Maximum/Tx-Enable
084
Window Register
Reference Trigger Offset Register 086
Timer Status Register
088
Cycle Counter Register
08A
Timer Counter Register
08C
Cycle Time Register
090
Reference Mark Register
094
Timer Compare Match Register 0 098
Timer Compare Match Register 1 09C
Timer Compare Match Register 2 0A0
Tx-Trigger Time Selection Register 0A4
Name
TTCR0
CMAX_TEW
RFTROFF
TSR
CCR
TCNTR
CYCTR
RFMK
TCMR0
TCMR1
TCMR2
TTTSEL
Access Size (bits)
Word (16)
Word (16)
Word (16)
Word (16)
Word (16)
Word (16)
Word (16)
Word (16)
Word (16)
Word (16)
Word (16)
Word (16)
Figure 19.12 RCAN-TL1 Timer registers
(1) Time Trigger Control Register0 (TTCR0)
The Time Trigger Control Register0 is a 16-bit read/write register and provides functions to
control the operation of the Timer. When operating in Time Trigger Mode, please refer to section
19.4.3 (1), Time Triggered Transmission.
• TTCR0 (Address = H'080)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TCR15 TCR14 TCR13 TCR12 TCR11 TCR10 -
-
- TCR6 TPSC5 TPSC4 TPSC3 TPSC2 TPSC1 TPSC0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R
R
R R/W R/W R/W R/W R/W R/W R/W
Rev. 2.00 Mar. 14, 2008 Page 966 of 1824
REJ09B0290-0200