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SH7263 Datasheet, PDF (1339/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series | |||
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Bit
DVST
CTRT
BEMP
Section 25 USB 2.0 Host/Function Module (USB)
Interrupt Name Cause of Interrupt
Function That
Generates the Related
Interrupt
Status
Device state
transition
interrupt
When a device state transition is
detected
⢠A USB bus reset detected
Function
DVSQ
⢠The suspend state detected
⢠Set address request received
⢠Set configuration request received
Control transfer When a stage transition is detected in
stage transition control transfer
interrupt
⢠Setup stage completed
Function
CTSQ
⢠Control write transfer status stage
transition
⢠Control read transfer status stage
transition
⢠Control transfer completed
⢠A control transfer sequence error
occurred
Buffer empty
interrupt
⢠When transmission of all of the
data in the buffer memory has
been completed
Host,
Function
BEMPSTS.
PIPEBEMP
⢠When an excessive maximum
packet size error has been
detected
Rev. 2.00 Mar. 14, 2008 Page 1305 of 1824
REJ09B0290-0200
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