SH7263 Datasheet, PDF (465/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Direct Memory Access Controller (DMAC)
(b) Burst Mode
In burst mode, once the DMAC obtains the bus mastership, it does not release the bus mastership
and continues to perform transfer until the transfer end condition is satisfied. In external request
mode with low level detection of the DREQ pin, however, when the DREQ pin is driven high, the
bus mastership is passed to another bus master after the DMAC transfer request that has already
been accepted ends, even if the transfer end conditions have not been satisfied.
Figure 10.11 shows DMA transfer timing in burst mode.
DREQ
Bus cycle
CPU
CPU CPU DMAC DMAC DMAC DMAC CPU
Read Write Read Write
CPU
Figure 10.11 DMA Transfer Example in Burst Mode
(Dual Address, DREQ Low Level Detection)
(3) Relationship between Request Modes and Bus Modes by DMA Transfer Category
Table 10.10 shows the relationship between request modes and bus modes by DMA transfer
category.
Table 10.10 Relationship of Request Modes and Bus Modes by DMA Transfer Category
Address
Mode Transfer Category
Request Bus Transfer
Usable
Mode Mode Size (Bits) Channels
Dual
External device with DACK and external External B/C 8/16/32/128 0 to 3
memory
External device with DACK and memory- External
mapped external device
External memory and external memory All*⁴
External memory and memory-mapped All*⁴
external device
Memory-mapped external device and All*⁴
memory-mapped external device
External memory and on-chip peripheral All*¹
module
Memory-mapped external device and All*¹
on-chip peripheral module
B/C 8/16/32/128 0 to 3
B/C 8/16/32/128 0 to 7*³
B/C 8/16/32/128 0 to 7*³
B/C 8/16/32/128 0 to 7*³
B/C*⁵ 8/16/32/128*² 0 to 7*³
B/C*⁵ 8/16/32/128*² 0 to 7*³
Rev. 2.00 Mar. 14, 2008 Page 431 of 1824
REJ09B0290-0200