SH7263 Datasheet, PDF (128/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 3 Floating-Point Unit (FPU)
3.3.2 Floating-Point Status/Control Register (FPSCR)
FPSCR is a 32-bit register that controls floating-point instructions, sets FPU exceptions, and
selects the rounding mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
QIS
-
SZ PR DN
Cause
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
R/W: R
R
R
R
R
R
R
R
R R/W R R/W R/W R R/W R/W
Bit: 15
Initial value: 0
R/W: R/W
14 13
Cause
0
0
R/W R/W
12
0
R/W
11
0
R/W
10 9
8
Enable
0
0
0
R/W R/W R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
Flag
0
R/W
3
0
R/W
2
0
R/W
1
RM1
0
R/W
0
RM0
1
R/W
Bit
Bit Name
31 to 23 —
Initial
Value
All 0
22
QIS
0
21
—
0
20
SZ
0
19
PR
0
18
DN
1
R/W _Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Nonnunerical Processing Mode
0: Processes qNaN or ±∞ as such
1: Treats qNaN or ±∞ as the same as sNaN (valid only
when FPSCR.Enable.V = 1)
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W Transfer Size Mode
0: Data size of FMOV instruction is 32-bits
1: Data size of FMOV instruction is a 32-bit register pair
(64 bits)
R/W Precision Mode
0: Floating-point instructions are executed as single-
precision operations
1: Floating-point instructions are executed as double-
precision operations (graphics support instructions
are undefined)
R
Denormalization Mode (Always fixed to 1 in SH2A-
FPU)
1: Denormalized number is treated as zero
Rev. 2.00 Mar. 14, 2008 Page 94 of 1824
REJ09B0290-0200