SH7263 Datasheet, PDF (1405/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 26 LCD Controller (LCDC)
26.3.2 LCDC Module Type Register (LDMTR)
LDMTR sets the control signals output from this LCDC and the polarity of the data signals,
according to the polarity of the signals for the LCD module connected to the LCDC.
Bit: 15 14 13 12 11 10 9
8
7
FLM
POL
CL1
POL
DISP
POL
DPOL
-
MCNT CL1CNTCL2CNT -
Initial value: 0
0
0
0
0
0
0
1
0
R/W: R/W R/W R/W R/W R R/W R/W R/W R
6
5
4
3
2
1
0
-
MIFTYP[5:0]
0
0
0
1
0
0
1
R R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
15
FLMPOL 0
R/W FLM (Vertical Sync Signal) Polarity Select
Selects the polarity of the LCD_FLM (vertical sync
signal, first line marker) for the LCD module.
0: LCD_FLM pulse is high active
1: LCD_FLM pulse is low active
14
CL1POL 0
R/W CL1 (Horizontal Sync Signal) Polarity Select
Selects the polarity of the LCD_CL1 (horizontal sync
signal) for the LCD module.
0: LCD_CL1 pulse is high active
1: LCD_CL1 pulse is low active
13
DISPPOL 0
R/W DISP (Display Enable) Polarity Select
Selects the polarity of the LCD_M_DISP (display
enable) for the LCD module.
0: LCD_M_DISP is high active
1: LCD_M_DISP is low active
12
DPOL
0
R/W Display Data Polarity Select
Selects the polarity of the LCD_DATA (display data) for
the LCD module. This bit supports inversion of the LCD
module.
0: LCD_DATA is high active, transparent-type LCD
panel
1: LCD_DATA is low active, reflective-type LCD panel
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 2.00 Mar. 14, 2008 Page 1371 of 1824
REJ09B0290-0200