SH7263 Datasheet, PDF (1472/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 Sampling Rate Converter (SRC)
Initial
Bit
Bit Name Value R/W Description
1, 0
IFTRG[1:0] 00
R/W Input FIFO Data Triggering Number
Specifies the condition in terms of the number on
which the IINT bit in the SRC status register
(SRCSTAT) is set to 1. When the number of data
units in the input FIFO becomes equal to or smaller
than the triggering number listed below, the IINT bit is
set to 1.
00: 0
01: 4
10: 8
11: 12
27.2.4 SRC Output Data Control Register (SRCODCTRL)
SRCODCTRL is a 16-bit readable/writable register that specifies whether to exchange the
channels for the output data, specifies the endian format of output data, enables/disables the
interrupt requests, and specifies the triggering number of data units.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
OCH OED OEN
-
-
-
-
-
-
OFTRG[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R R/W R/W R/W R
R
R
R
R
R R/W R/W
Initial
Bit
Bit Name Value R/W Description
15 to 11 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
10
OCH
0
R/W Output Data Channel Exchange
Specifies whether to exchange the channels for the
SRC output data register (SRCOD). When processing
monaural data, do not set this bit to 1.
0: Does not exchange the channels (the same order
as data input)
1: Exchanges the channels (the opposite order from
data input)
Rev. 2.00 Mar. 14, 2008 Page 1438 of 1824
REJ09B0290-0200