SH7263 Datasheet, PDF(1097/1862 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

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SH7263 Datasheet, PDF (1097/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

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Section 20 IEBusTM Controller (IEB)

20.3.22 IEBus Receive Data Buffer 001 to 128 (IERB001 to IERB128)

IERB001 to IERB128 are 128-byte (8 Ã 128) buffers to which data to be transmitted during slave

transmission is written.

The initial values in IERB001 to IERB128 are undefined.

Bit: 7

6

5

4

3

2

1

0

RBn

Initial value: -

-

-

-

-

-

-

-

R/W: R* R* R* R* R* R* R* R*

[Legend]

n = 001 to 128

Initial

Bit

Bit Name Value

R/W Description

7 to 0 RBn

Undefined R* IEBus Receive Data Buffer

Data in RB001 to RB128 can be read when the RXBSY

bit in the IEBus receive status register (IERSR) is set to

1. Data read from RB001 to RB128 is the field data

during slave receive.

Receive data is written starting with RB001 for the start

1-byte data, followed by RB002 and RB003 and so on,

and RB128 stores the last data.

Note: * Reading these bits during slave reception (SRE in IEFLG is 1 and RXBSY in IERSR is

0) is prohibited. (Read value is undefined.)

Rev. 2.00 Mar. 14, 2008 Page 1063 of 1824

REJ09B0290-0200

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