SH7263 Datasheet, PDF (377/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
(9) Relationship between Refresh Requests and Bus Cycles
If a refresh request occurs during bus cycle execution, the refresh cycle must wait for the bus cycle
to be completed. If a refresh request occurs while the bus is released by the bus arbitration
function, the refresh will not be executed until the bus mastership is acquired. This LSI has the
REFOUT pin to request the bus while waiting for refresh execution. For REFOUT pin function
selection, see section 29, Pin Function Controller (PFC). This LSI continues to assert REFOUT
(low level) until the bus is acquired.
On receiving the asserted REFOUT signal, the external device must negate the BREQ signal and
return the bus. If the external bus does not return the bus for a period longer than the specified
refresh interval, refresh cannot be executed and the SDRAM contents may be lost.
If a new refresh request occurs while waiting for the previous refresh request, the previous refresh
request is deleted. To refresh correctly, a bus cycle longer than the refresh interval or the bus
mastership occupation must be prevented from occurring.
If a bus mastership is requested during self-refresh, the bus will not be released until the refresh is
completed.
Rev. 2.00 Mar. 14, 2008 Page 343 of 1824
REJ09B0290-0200