SH7263 Datasheet, PDF (389/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
T1
T2
CKIO
A25 to A0
CSn
WEn
Read
RD/WR
RD
D31 to D0
Write
RD/WR
RD
High
D31 to D0
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.36 Basic Access Timing for SRAM with Byte Selection (BAS = 0)
Rev. 2.00 Mar. 14, 2008 Page 355 of 1824
REJ09B0290-0200