SH7263 Datasheet, PDF (221/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 6 Interrupt Controller (INTC)
6.10 Usage Note
6.10.1 Timing to Clear an Interrupt Source
The interrupt source flags should be cleared in the interrupt exception service routine. After
clearing the interrupt source flag, "time from occurrence of interrupt request until interrupt
controller identifies priority, compares it with mask bits in SR, and sends interrupt request signal
to CPU" shown in table 6.5 is required before the interrupt source sent to the CPU is actually
cancelled. To ensure that an interrupt request that should have been cleared is not inadvertently
accepted again, read* the interrupt source flag after it has been cleared, and then execute an RTE
instruction.
Note: * When clearing the USB interrupt source flag, read the flag three times after clearing it.
6.10.2 Timing of IRQOUT Negation
Once the interrupt controller has accepted an interrupt request, the low level is output from the
IRQOUT pin until the CPU jumps to the first address of the interrupt exception service routine,
after which the high level is output from the IRQOUT pin.
If, however, the interrupt controller has accepted an interrupt request and the low level is being
output from the IRQOUT pin, but the interrupt request is canceled before the CPU has jumped to
the first address of the interrupt exception service routine, the low level continues to be output
from the IRQOUT pin until the CPU has jumped to the first address of the interrupt exception
service routine for the next interrupt request.
Rev. 2.00 Mar. 14, 2008 Page 187 of 1824
REJ09B0290-0200