SH7263 Datasheet, PDF (1246/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 24 AND/NAND Flash Memory Controller (FLCTL)
24.3.12 Control Code FIFO Register (FLECFIFO)
FLECFIFO is used to read or write the control code FIFO area.
In DMA transfer, data in this register must be specified as the destination (source). When
transferring 16-byte DMA, access FLECFIFO from the address on the 16-byte address boundary.
Note that the direction of read or write specified by the SELRW bit in FLCMDCR must match
that specified in this register. When changing the read/write direction, FLECFIFO should be
cleared by setting the AC1CLR bit in FLINTDMACR before use.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECFO[31:16]
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
ECFO[15:0]
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit Bit Name Value
R/W
31 to 0 ECFO[31:0] H'xxxxxxxx R/W
Description
Control Code FIFO Area Read/Write Data
In write: Data is written to the control code FIFO area.
In read: Data in the control code FIFO area is read.
Rev. 2.00 Mar. 14, 2008 Page 1212 of 1824
REJ09B0290-0200