SH7263 Datasheet, PDF (1857/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

S
SACK interrupt..................................... 1321
Sampling rate converter (SRC)............. 1433
Saving to bank ........................................ 181
Saving to stack........................................ 183
Scan mode ............................................ 1165
SCIF interrupt sources ............................ 777
SCIF timing .......................................... 1740
SD host interface (SDHI)...................... 1453
SDHI timing ......................................... 1762
SDRAM interface ................................... 308
Searching cache ...................................... 220
Sector access mode ............................... 1222
Self-refreshing ........................................ 341
Sending a break signal ............................ 779
Serial bit clock control............................ 903
Serial communication interface
with FIFO (SCIF) ................................... 713
Serial Sound Interface (SSI) ................... 867
Setting analog input voltage ....... 1173, 1183
Setting I/O ports for RCAN-TL1.......... 1008
Setting the display resolution................ 1413
Shift instructions....................................... 75
Sign extension of word data ..................... 48
SIGN interrupt ...................................... 1322
Single address mode ............................... 428
Single mode .......................................... 1160
Single read .............................................. 328
Single write............................................. 331
Slave receive operation........................... 852
Slave transmit operation ......................... 849
Sleep mode ................................... 983, 1578
Slot illegal instructions ........................... 134
SOF interpolation function ................... 1358
Software standby mode......................... 1579
SRAM interface with byte selection ....... 354
SSI timing ............................................. 1746
SSU Interrupt sources ............................. 822
SSU mode ............................................... 805
SSU timing............................................ 1741
Stack after interrupt exception
handling .................................................. 173
Stack status after exception handling
ends ......................................................... 138
Standby control circuit............................ 102
Status register (SR) ................................... 42
Stopping and resuming CD-DSP
operation .............................................. 1148
Supported DMA transfers ....................... 425
Synchronous serial communication unit
(SSU) ...................................................... 783
Syndrome calculation............................ 1138
System control instructions....................... 77
System matrix ......................................... 929
T
T bit........................................................... 49
TAP controller ...................................... 1597
Target-sector buffering function ........... 1142
TDO output timing................................ 1598
Test mode settings................................... 980
Time slave............................................... 994
Time trigger control (TT control) ........... 925
Time triggered transmission.................... 989
Timestamp .............................................. 924
Timing to clear an interrupt source ......... 187
Transfer clock ......................................... 800
Transfer rate............................................ 831
Trap instructions ..................................... 134
TTW[1:0] (time trigger window) ............ 926
Tx-trigger control field ........................... 926
Tx-trigger time (TTT) ............................. 925
Types of exception handling
and priority order .................................... 117
U
UBC timing........................................... 1736
Unconditional branch instructions
with no delay slot ...................................... 49
Rev. 2.00 Mar. 14, 2008 Page 1823 of 1824
REJ09B0290-0200