SH7263 Datasheet, PDF (771/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
• Clock synchronous mode:
N=
Pφ
8 × 2^2n-1 × B
×
10⁶
−1
B:
Bit rate (bits/s)
N:
SCBRR setting for baud rate generator (0 ≤ N ≤ 255)
(The setting must satisfy the electrical characteristics.)
Pφ: Operating frequency for peripheral modules (MHz)
n:
Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n,
see table 15.3.)
Table 15.3 SCSMR Settings
n
Clock Source
0
Pφ
1
Pφ/4
2
Pφ/16
3
Pφ/64
CKS[1]
0
0
1
1
SCSMR Settings
CKS[0]
0
1
0
1
The bit rate error in asynchronous mode is given by the following formula:
When baud rate generator operates in normal mode (the BGDM bit of SCEMR is 0):
Error (%) =
Pφ × 10⁶
− 1 _{× 100 (Operation on a base clock with a frequency of}
(N + 1) × B × 64 × 2^2n-1
16 times the bit rate)
Error (%) =
Pφ × 10⁶
−1
(N + 1) × B × 32× 2^2n-1
× 100
(Operation on a base clock with a frequency of
8 times the bit rate)
When baud rate generator operates in double speed mode (the BGDM bit of SCEMR is 1):
Error (%) =
Pφ × 10⁶
−1
(N + 1) × B × 32× 2^2n-1
× 100
(Operation on a base clock with a frequency of
16 times the bit rate)
Error (%) =
Pφ × 10⁶
−1
(N + 1) × B × 16× 2^2n-1
× 100
(Operation on a base clock with a frequency of
8 times the bit rate)
Rev. 2.00 Mar. 14, 2008 Page 737 of 1824
REJ09B0290-0200