SH7263 Datasheet, PDF (1822/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Main Revisions for this Edition
Item
15.3.9 FIFO Control
Register (SCFCR)
16.3.1 SS Control
Register H (SSCRH)
16.3.2 SS Control
Register L (SSCRL)
Page
748
788
789
Revision (See Manual for Details)
Table amended
Initial
Bit
Bit Name Value R/W Description
3
MCE
0
R/W Modem Control Enable
Enables modem control signals CTS and RTS.
For channels 0 to 2 in clock synchronous mode, MCE bit
should always be 0.
0: Modem signal disabled*
1: Modem signal enabled
Note: * The CTS level has no effect on transmit
operation, regardless of the input value, and
the RTS level has no effect on receive
operation.
Table amended
Bit
Bit Name Value R/W
1, 0 CSS[1:0] 01
R/W
Description
SCS Pin Select
Select that the SCS pin functions as SCS input or
output.
00: Setting prohibited
01: Setting prohibited
10: Function as SCS automatic input/output (function as
SCS input before and after transfer and output a low
level during transfer)
11: Function as SCS automatic output (outputs a high
level before and after transfer and outputs a low
level during transfer)
Bit table amended
Bit: 7
6
5
4
3
2
1
0
- SSUMS SRES -
-
-
DATS[1:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R R/W R/W R
R
R R/W R/W
Table amended
Initial
Bit
Bit Name Value R/W
Description
7
⎯
0
R/W
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 2.00 Mar. 14, 2008 Page 1788 of 1824
REJ09B0290-0200