SH7263 Datasheet, PDF (194/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 6 Interrupt Controller (INTC)
Table 6.4 Interrupt Exception Handling Vectors and Priorities
Interrupt Source
NMI
User break
H-UDI
IRQ IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
PINT PINT0
PINT1
PINT2
PINT3
PINT4
Interrupt Vector
Vector
Interrupt
Vector Table Priority
Corresponding
Address Offset (Initial Value) IPR (Bit)
IPR
Setting
Unit
Internal
Priority
Default
Priority
11
H'0000002C to 16
⎯
H'0000002F
⎯
High
12
H'00000030 to 15
⎯
⎯
H'00000033
14
H'00000038 to 15
⎯
⎯
H'0000003B
64
H'00000100 to 0 to 15 (0) IPR01 (15 to 12) ⎯
H'00000103
65
H'00000104 to 0 to 15 (0) IPR01 (11 to 8) ⎯
H'00000107
66
H'00000108 to 0 to 15 (0) IPR01 (7 to 4) ⎯
H'0000010B
67
H'0000010C to 0 to 15 (0) IPR01 (3 to 0) ⎯
H'0000010F
68
H'00000110 to 0 to 15 (0) IPR02 (15 to 12) ⎯
H'00000113
69
H'00000114 to 0 to 15 (0) IPR02 (11 to 8) ⎯
H'00000117
70
H'00000118 to 0 to 15 (0) IPR02 (7 to 4) ⎯
H'0000011B
71
H'0000011C to 0 to 15 (0) IPR02 (3 to 0) ⎯
H'0000011F
80
H'00000140 to 0 to 15 (0) IPR05 (15 to 12) 1
H'00000143
81
H'00000144 to
2
H'00000147
82
H'00000148 to
3
H'0000014B
83
H'0000014C to
4
H'0000014F
84
H'00000150 to
H'00000153
5
Low
Rev. 2.00 Mar. 14, 2008 Page 160 of 1824
REJ09B0290-0200