SH7263 Datasheet, PDF (925/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 18 Serial Sound Interface (SSI)
SCKP = 0, SWSP = 0, DEL = 0, CHNL = 11, SPDP = 0, SDTA = 1
System word length = data word length × 4
SSISCK
SSIWS
SSIDATA
MSB
LSB MSB
LSB MSB
LSB MSB
LSB
Data
word 1
Data
word 2
Data
word 3
Data
word 4
MSB
LSB MSB
LSB MSB
LSB MSB
LSB
Data
word 5
Data
word 6
Data
word 7
Data
word 8
System word 1
System word 2
Figure 18.9 Multi-Channel Format (8 channels; transmitted and received in
the order of padding bits and serial data; with padding)
(7) Bit Setting Configuration Format
Several more configuration bits in non-compressed mode are shown below. These bits are not
mutually exclusive, but some combinations may not be useful for any other device.
These configuration bits are described below with reference to figure 18.10.
SWL = 6 bits (not attainable in SSI module, demonstration only)
DWL = 4 bits (not attainable in SSI module, demonstration only)
CHNL = 00, SCKP = 0, SWSP = 0, SPDP = 0, SDTA = 0, PDTA = 0, DEL = 0, MUEN = 0
4-bit data samples continuously written to SSITDR are transmitted onto the serial audio bus.
SSISCK
SSIWS
1st channel
2nd channel
SSIDATA TD28 0 0 TD31 TD30 TD29 TD28 0 0 TD31 TD30 TD29 TD28 0 0 TD31
Key for this and following diagrams:
Arrow head indicates sampling point of receiver
TDn
Bit n in SSITDR
0
means a low level on the serial bus (padding or mute)
1
means a high level on the serial bus (padding)
Figure 18.10 Basic Sample Format
(Transmit Mode with Example System/Data Word Length)
Rev. 2.00 Mar. 14, 2008 Page 891 of 1824
REJ09B0290-0200