SH7263 Datasheet, PDF (349/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
Table 9.12 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address
Multiplex Output (2)-1
Setting
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
11 (32 bits)
01 (12 bits)
01 (9 bits)
Output Pin of Row Address Column Address
This LSI
Output Cycle Output Cycle
SDRAM Pin
Function
A17
A26
A17
Unused
A16
A25
A16
A15
A24*²
A24*²
A14
A23*²
A23*²
A13 (BA1)
A12 (BA0)
Specifies bank
A13
A22
A12
A21
A13
L/H*¹
A11
A10/AP
Address
Specifies
address/precharge
A11
A20
A11
A9
Address
A10
A19
A10
A8
A9
A18
A9
A7
A8
A17
A8
A6
A7
A16
A7
A5
A6
A15
A6
A4
A5
A14
A5
A3
A4
A13
A4
A2
A3
A12
A3
A1
A2
A11
A2
A0
A1
A10
A1
Unused
A0
A9
A0
Example of connected memory
256-Mbit product (2 Mwords × 32 bits × 4 banks, column 9 bits product): 1
128-Mbit product (2 Mwords × 16 bits × 4 banks, column 9 bits product): 2
Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the
access mode.
2. Bank address specification
3. Only the RASL pin is asserted because the A25 pin specified the bank address. RASU
is not asserted.
Rev. 2.00 Mar. 14, 2008 Page 315 of 1824
REJ09B0290-0200