SH7263 Datasheet, PDF (450/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Direct Memory Access Controller (DMAC)
10.4.2 DMA Transfer Requests
DMA transfer requests are basically generated in either the data transfer source or destination, but
they can also be generated in external devices and on-chip peripheral modules that are neither the
transfer source nor destination.
Transfers can be requested in three modes: auto request, external request, and on-chip peripheral
module request. The request mode is selected by the RS[3:0] bits in CHCR_0 to CHCR_7 and
DMARS0 to DMARS3.
(1) Auto-Request Mode
When there is no transfer request signal from an external source, as in a memory-to-memory
transfer or a transfer between memory and an on-chip peripheral module unable to request a
transfer, the auto-request mode allows the DMAC to automatically generate a transfer request
signal internally. When the DE bits in CHCR_0 to CHCR_7 and the DME bit in DMAOR are set
to 1, the transfer begins so long as the TE bits in CHCR_0 to CHCR_7, and the AE and NMIF bits
in DMAOR are 0.
(2) External Request Mode
In this mode a transfer is performed at the request signals (DREQ0 to DREQ3) of an external
device. Choose one of the modes shown in table 10.5 according to the application system. When
the DMA transfer is enabled (DE = 1, DME = 1, TEMASK = 0 or 1 (TE = 0 when TEMASK = 0),
AE = 0, NMIF = 0 for level detection; DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0 for edge
detection), DMA transfer is performed upon a request at the DREQ input.
Table 10.5 Selecting External Request Modes with the RS Bits
RS[3] RS[2] RS[1] RS[0] Address Mode
Transfer Source
Transfer
Destination
0
0
0
0
Dual address mode Any
Any
0
0
1
0
Single address mode External memory, External device with
memory-mapped DACK
external device
1
External device with External memory,
DACK
memory-mapped
external device
Rev. 2.00 Mar. 14, 2008 Page 416 of 1824
REJ09B0290-0200