SH7263 Datasheet, PDF (368/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
CKIO
A25 to A0
A12/A11*¹
CS3
RASL, RASU
CASL, CASU
RD/WR
DQMxx
D31 to D0
BS
DACKn*²
Td1
Td2
Td3
Td4
Tnop Tc1
Tc2
Tc3
Tc4
Tde
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.23 Burst Read Timing (Bank Active, Same Row Addresses in the Same Bank, CAS
Latency 1)
Rev. 2.00 Mar. 14, 2008 Page 334 of 1824
REJ09B0290-0200