SH7263 Datasheet, PDF (1008/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-TL1)
Bit0: TSR0
0
1
Description
Timer (TCNTR) has not overrun in event-trigger mode (Initial value)
Time reference message with Next_is_Gap has not been received in time-
trigger mode message error has not occurred in test mode.
[Clearing condition] Writing ‘1’ to IRR13
[Setting condition]
Timer (TCNTR) has overrun and changed from H'FFFF to H'0000 in event-
trigger mode.time reference message with Next_is_Gap has been received
in time-trigger mode message error has occurred in test mode
(5) Cycle Counter Register (CCR)
This register is a 6-bit read/write register. Its purpose is to store the number of the basic cycle for
Time -Triggered Transmissions. Its value is updated in different fashions depending if RCAN-TL1
is programmed to work as a potential time master or as a time slave. If RCAN-TL1 is working as
(potential) time master, CCR is:
⎯ Incremented by one every time the cycle time (CYCTR) matches to Tx-Trigger Time of
Mailbox-30 or
⎯ Overwritten with the value contained in MSG_DATA_0[5:0] of Mailbox 31 when a valid
reference message is received.
If RCAN-TL1 is working as a time slave, CCR is only overwritten with the value of
MSG_DATA_0[5:0] of Mailbox 31 when a valid reference message is received.
If CMAX = 3'111, CCR is always H'0000.
• CCR (Address = H'08A)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
CCR[5:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W
Bits 15 to 6: Reserved. The written value should always be ‘0’ and the returned value is ‘0’.
Bit 5 to 0 — Cycle Counter Register (CCR): Indicates the number of the current Base Cycle of
the matrix cycle for Timer Triggered transmission.
Rev. 2.00 Mar. 14, 2008 Page 974 of 1824
REJ09B0290-0200