SH7263 Datasheet, PDF (1033/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-TL1)
(1) Clear TCNTR by TCMR0 in Event-Trigger mode
TCMR0
n
TCNTR
n-2
n-1
n
0
1
2
3
(2) Interrupt generation by TCMR0/1/2 in Event-Trigger mode
TCMR0/1/2
n
TCNTR
n-2
n-1
n
n+1
n+2
n+3
n+4
Flag/interrupt
(3) Interrupt generation by TCMR0 in Time-Trigger mode
TCMR0
n
TCNTR
n-2
n-1
n
n+1
n+2
n+3
n+4
Flag/interrupt
(4) Interrupt generation by TCMR1/2 in Time-Trigger mode
TCMR0/1/2
n
CYCTR
n-2
n-1
n
n+1
n+2
n+3
n+4
Flag/interrupt
(5) Time-triggered transmission request in Time-Trigger mode, during bus idle
Tx-Trigger Time I
CYCTR
TEW (register value)
TEW counter
Transmission request
for MBI
Transmitted message
n-1
n
n
n+1
n+2
n+3
n+4
n+5
2
0
1
2
0
SOF
Delay = (1 Bit Timing + 8 clocks)
to (2 Bit Timings + 11 clocks)
Figure 19.23 Timing Diagram of Timer
During merged arbitrating window, event-trigger transmission is served after completion of time-
triggered transmission. For example, If transmission of Mailbox-25 is completed and CYCTR
doesn't reach TTT26, event-trigger transmission starts based on message transmission priority
specified by MCR2. TXPR of time-triggered transmission is not cleared after transmission
completion, however, that of event-triggered transmission is cleared.
Rev. 2.00 Mar. 14, 2008 Page 999 of 1824
REJ09B0290-0200