SH7263 Datasheet, PDF (1423/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 26 LCD Controller (LCDC)
26.3.16 LCDC Interrupt Control Register (LDINTR)
LDINTR specifies where to control the Vsync interrupt of the LCD module. See also section
26.3.20, LCDC User Specified Interrupt Control Register (LDUINTR) and section 26.3.21, LCDC
User Specified Interrupt Line Number Register (LDUINTLNR) for interrupts. Note that
operations by this register setting and LCDC user specified interrupt control register (LDUINTR)
setting are independent.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
MINT
EN
FINT
EN
VSINT
EN
VEINT
EN
MINTS
FINTS VSINTS VEINTS
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R
R
R
R
R
R
R
R
Initial
Bit
Bit Name Value R/W Description
15
MINTEN 0
R/W Memory Access Interrupt Enable
Enables or disables an interrupt generation at the start
point of each vertical retrace line period for VRAM
access by LCDC.
0: Disables an interrupt generation at the start point of
each vertical retrace line period for VRAM access
1: Enables an interrupt generation at the start point of
each vertical retrace line period for VRAM access
14
FINTEN
0
R/W Frame End Interrupt Enable
Enables or disables the generation of an interrupt after
the last pixel of a frame is output to LDC panel.
0: Disables an interrupt generation when the last pixel
of the frame is output
1: Enables an interrupt generation when the last pixel of
the frame is output
13
VSINTEN 0
R/W Vsync Starting Point Interrupt Enable
Enables or disables the generation of an interrupt at the
start point of LCDC's Vsync.
0: Interrupt at the start point of the Vsyncl is disabled
1: Interrupt at the start point of the Vsync is enabled
Rev. 2.00 Mar. 14, 2008 Page 1389 of 1824
REJ09B0290-0200