SH7263 Datasheet, PDF (533/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.18 Timer Output Control Register 2 (TOCR2)
TOCR2 is an 8-bit readable/writable register that controls output level inversion of PWM output
in complementary PWM mode and reset-synchronized PWM mode.
Bit: 7
6
5
4
3
2
1
0
BF[1:0] OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name value R/W Description
7, 6 BF[1:0]
00
R/W TOLBR Buffer Transfer Timing Select
These bits select the timing for transferring data from
TOLBR to TOCR2.
For details, see table 11.30.
5
OLS3N
0
R/W Output Level Select 3N*
This bit selects the output level on TIOC4D in reset-
synchronized PWM mode/complementary PWM mode.
See table 11.31.
4
OLS3P
0
R/W Output Level Select 3P*
This bit selects the output level on TIOC4B in reset-
synchronized PWM mode/complementary PWM mode.
See table 11.32.
3
OLS2N
0
R/W Output Level Select 2N*
This bit selects the output level on TIOC4C in reset-
synchronized PWM mode/complementary PWM mode.
See table 11.33.
2
OLS2P
0
R/W Output Level Select 2P*
This bit selects the output level on TIOC4A in reset-
synchronized PWM mode/complementary PWM mode.
See table 11.34.
1
OLS1N
0
R/W Output Level Select 1N*
This bit selects the output level on TIOC3D in reset-
synchronized PWM mode/complementary PWM mode.
See table 11.35.
Rev. 2.00 Mar. 14, 2008 Page 499 of 1824
REJ09B0290-0200