SH7263 Datasheet, PDF (146/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 4 Clock Pulse Generator (CPG)
4.5 Changing the Frequency
The frequency of the internal clock (Iφ) and peripheral clock (Pφ) can be changed either by
changing the multiplication rate of PLL circuit or by changing the division rates of divider. All of
these are controlled by software through the frequency control register (FRQCR). The methods are
described below.
4.5.1 Changing the Multiplication Rate
Oscillation settling time must be provided when the multiplication rate of the PLL circuit is
changed. The on-chip WDT counts the settling time. The oscillation settling time is the same as
when software standby mode is canceled.
1. In the initial state, the multiplication rate of PLL circuit is 8 time.
2. Set a value that will become the specified oscillation settling time in the WDT and stop the
WDT. The following must be set:
WTCSR.TME = 0: WDT stops
WTCSR.CKS[2:0]: Division ratio of WDT count clock
WTCNT counter: Initial counter value
(The WDT count is incremented using the clock after the setting.)
3. Set the desired value in the STC1 and STC0 bits. The division ratio can also be set in the IFC
and PFC2 to PFC0 bits.
4. This LSI pauses temporarily and the WDT starts incrementing. The internal and peripheral
clocks both stop and the WDT is supplied with the clock. The clock will continue to be output
at the CKIO pin. This state is the same as software standby mode. Whether or not registers are
initialized depends on the module. For details, see section 34.3, Register States in Each
Operating Mode.
5. Supply of the clock that has been set begins at WDT count overflow, and this LSI begins
operating again. The WDT stops after it overflows.
Rev. 2.00 Mar. 14, 2008 Page 112 of 1824
REJ09B0290-0200