SH7263 Datasheet, PDF (1277/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
25.3.4 Test Mode Register (TESTMODE)
TESTMODE is a register that controls the USB test signal output and the module’s internal USB
transceiver during high-speed operation. This register is initialized by a power-on reset. A
software reset initializes the UTST bits.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
HOST
PCC
-
-
-
-
-
-
-
-
-
-
-
UTST[3:0]
Initial value: 0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
R/W: R/W R R R R R R R R R R R R/W R/W R/W R/W
Bit
Bit Name
15
HOSTPCC
14 to 9 ⎯
8
⎯
7 to 4 ⎯
Initial
Value
0
All 0
1
All 0
R/W Description
R/W Disconnect Detector Power Switching
Sets the USB transceiver*.
This bit can only be set if the UACKEY0 and
UACKEY1 bits in the device control register have
been set.
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R
Reserved
The value of this bit when read depends on the
values of the UACKEY0 and UACKEY1 bits. When
UACKEY0 and UACKEY1 are both cleared to 0, it is
always read as 1, and writing to this bit has no effect.
When UACKEY0 is cleared to 0 and UACKEY1 is set
to 1, it is always read as 0. In this case, the write
value should also always be 0.*
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Mar. 14, 2008 Page 1243 of 1824
REJ09B0290-0200