SH7263 Datasheet, PDF (1343/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
Table 25.12 Conditions under which a BRDY Interrupt is Generated
Access Transfer
Direction Direction Pipe
Reading Receive DCP
1 to 7
Conditions under which BRDY Interrupt is
BFRE DBLB Generated
⎯
0
(1) or (2) below:
(1) Short packet reception, including a zero-
length packet
(2) Buffer is full by reception
0
0
(1), (2) or (3) below:
(1) Short packet reception, including a zero-
length packet
(2) Buffer is full* by reception
(3) Transaction counter ends when buffer is not
full.
1
(1), (2), (3) or (4) below:
(1) One of (a) to (c) conditions occurs when
both buffers are waiting for reception:
(a) Short packet reception, including a zero-
length packet
(b) One buffer of two is full* by reception
(c) Transaction counter ends when buffer is
not full.
(2) Reading of one buffer is complete when
both buffers are waiting for reading.
(3) Software sets the BCLR bit to 1 to clear
receive data in one buffer when both buffers
are waiting for reading.
(4) The TGL bit in CFIFOSIE is set to 1 in
continuous transfer mode (the CNTMD bit in
PIPECFG is set to 1) when the buffer on the
SIE side has data.
Rev. 2.00 Mar. 14, 2008 Page 1309 of 1824
REJ09B0290-0200