SH7263 Datasheet, PDF (1828/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Main Revisions for this Edition
Item
16.4.5 SSU Mode
Figure 16.8 Flowchart
Example of Data
Reception (SSU Mode)
Page
811
(4) Data
812
Transmission/Reception
Figure 16.9 Flowchart 813
Example of
Simultaneous
Transmission/Reception
(SSU Mode)
16.4.7 Clock
816
Synchronous
Communication Mode
(2) Data Transmission
Figure 16.13 Example
of Transmission
Operation (Clock
Synchronous
Communication Mode)
Revision (See Manual for Details)
Figure amended
[3], [6] Receive error processing:
When a receive error occurs, execute the designated error
processing after reading the ORER bit in SSSR. After that,
clear the ORER bit to 0. While the ORER bit is set to 1,
reception is not resumed.
Description added
… The data transmission/reception is started by writing
transmit data to SSTDR with TE = RE = 1. When the RDRF bit
is set to 1, at the 8th rising edge of the transfer clock the ORER
bit in SSSR is set to 1, an overrun error (SSERI) is generated,
and both transmission and reception are stopped.
Transmission and reception are not possible while the ORER
bit is set to 1. To resume transmission and reception, clear the
ORER bit to 0.
Figure amended
[3] Check the SSU state:
Read SSSR confirming that the RDRF bit is 1.
A change of the RDRF bit (from 0 to 1) can be notified
by SSRXI interrupt.
Description amended
… After that, the SSU sets the TDRE bit to 1 and starts
transmission. At this time, if the TIE bit in SSER is set to 1, a
transmit-data-empty SSTXI interrupt is generated.
When 1-frame data has been transferred with TDRE = 0, the
SSTDR contents are transferred to SSTRSR to start the next
frame transmission. When the 8th bit of transmit data has been
transferred with TDRE = 1, the TEND bit in SSSR is set to 1
and the state is retained. At this time, if the TEIE bit in SSER is
set to 1, a transmit-end SSTXI interrupt is generated.
Figure amended
TEND
LSI operation
User operation
SSTXI interrupt
generated
Data written
to SSTDR
Data written
to SSTDR
SSTXI interrupt
generated
SSTXI interrupt
generated
Rev. 2.00 Mar. 14, 2008 Page 1794 of 1824
REJ09B0290-0200