SH7263 Datasheet, PDF (1118/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
Figure 21.5 is a schematic diagram of the stream-data output control block.
On recognizing that one sector of CD-ROM data is ready in the core of the CD-ROM decoder, this
block ensures that the output stream-data register in the bus bridge section is empty and then starts
to acquire the data for output from the core of the CD-ROM decoder.
Output
stream data
Output stream-data
control signal
Output stream-data
protocol controller
Figure 21.5 Schematic Diagram of the Stream-Data Output Control Block
This block has functions related to INTC interrupts and DMAC activation control such as
suspending and masking of interrupts, turning interrupt flags off after they are read, asserting the
activation signal to the DMAC, and negating the activation signal according to the detected
amount of data that has been transferred.
Rev. 2.00 Mar. 14, 2008 Page 1084 of 1824
REJ09B0290-0200