SH7263 Datasheet, PDF (1403/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 26 LCD Controller (LCDC)
Register Name
Abbreviation R/W
LCDC power supply sequence LDPSPR
R/W
period register
LCDC control register
LDCNTR
R/W
LCDC user specified interrupt LDUINTR
R/W
control register
LCDC user specified interrupt LDUINTLNR R/W
line number register
LCDC memory access interval LDLIRNR
R/W
number register
Initial Value Address
H'F60F
H'FFFFFC26
H'0000
H'0000
H'FFFFFC28
H'FFFFFC34
H'004F
H'FFFFFC36
H'0000
H'FFFFFC40
Access
Size
16
16
16
16
16
26.3.1 LCDC Input Clock Register (LDICKR)
This LCDC can select bus clock, the peripheral clock, or the external clock as its operation clock
source. The selected clock source can be divided using an internal divider into a clock of 1/1 to
1/32 and be used as the LCDC operating clock (DOTCLK). The clock output from the LCDC is
used to generate the synchronous clock output (LCD_CL2) for the LCD panel from the operating
clock selected in this register. For a TFT panel, LCD_CL2 = DOTCLK, and for an STN or DSTN
panel, LCD_CL2 = a clock with a frequency of (DOTCLK/data bus width of output to LCD
panel). The LDICKR must be set so that the clock input to the LCDC is 66 MHz or less regardless
of the LCD_CL2.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
ICKSEL[1:0]
-
-
-
-
-
-
DCDR[5:0]
Initial value: 0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
R/W: R
R R/W R/W R
R
R
R
R
R R/W R/W R/W R/W R/W R/W
Bit
15, 14
Bit Name
⎯
Initial
Value R/W
All 0 R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00 Mar. 14, 2008 Page 1369 of 1824
REJ09B0290-0200