SH7263 Datasheet, PDF (266/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
6. PCMCIA direct interface
⎯ Supports the IC memory card and I/O card interface defined in JEIDA specifications Ver.
4.2 (PCMCIA2.1 Rev. 2.1).
⎯ Wait-cycle insertion controllable by program.
7. SRAM interface with byte selection
⎯ Can connect directly to a SRAM with byte selection.
8. Burst MPX-I/O interface
⎯ Can connect directly to a peripheral LSI that needs an address/data multiplexing.
⎯ Supports burst transfer.
9. Burst ROM interface (clocked synchronous)
⎯ Can connect directly to a ROM of the clocked synchronous type.
10. Bus arbitration
⎯ Shares all of the resources with other CPU and outputs the bus enable after receiving the
bus request from external devices.
11. Refresh function
⎯ Supports the auto-refresh and self-refresh functions.
⎯ Specifies the refresh interval using the refresh counter and clock selection.
⎯ Can execute concentrated refresh by specifying the refresh counts (1, 2, 4, 6, or 8).
12. Usage as interval timer for refresh counter
⎯ Generates an interrupt request at compare match.
Rev. 2.00 Mar. 14, 2008 Page 232 of 1824
REJ09B0290-0200