SH7263 Datasheet, PDF (1032/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-TL1)
The following settings were used in the above example:
rep_factor
(register)
Mailbox-24 3'b001
Mailbox-25 3'b000
Mailbox-26 3'b000
Mailbox-27 3'b000
Mailbox-28 3'b010
Mailbox-29 3'b011
Mailbox-30 ⎯
Mailbox-31 ⎯
CMAX = 3'b011, TXPR[30] = 0
Offset
6'b000000
6'b000000
6'b000000
6'b000000
6'b000001
6'b000110
⎯
⎯
TTW[1:0]
2'b00
2'b10
2'b10
2'b11
2'b00
2'b01
⎯
⎯
MBC[2:0]
3'b000
3'b000
3'b000
3'b000
3'b000
3'b000
3'b111
3'b011
During merged arbitrating window, request by time-triggered transmission is served in the way of
FCFS (First Come First Served). For example, if Mailbox-25 cannot be transmitted between Tx-
Trigger Time 25 (TTT25) and TTT26, Mailbox-25 has higher priority than Mailbox-26 between
TTT26 and 28.
MBC needs to be set into 3'b111, in order to disable time-triggered transmission. If RCAN-TL1 is
Time Master, MBC[30] has to be 3'b000 and time reference window is automatically recognized
as arbitrating window.
• Timer Operation
Figure 19.23 shows the timing diagram of the timer. By setting Tx-Trigger Time = n, time trigger
transmission starts between CYCTR = n + 2 and
CYCTR = n + 3.
Rev. 2.00 Mar. 14, 2008 Page 998 of 1824
REJ09B0290-0200