SH7263 Datasheet, PDF (1650/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 34 List of Registers
Module
Name Register Name
Abbreviation
Number
of Bits Address
RCAN- Cycle Time Register_1
TL1
Reference Mark Register_1
CYCTR_1
RFMK_1
16
H'FFFF0890
16
H'FFFF0894
Timer Compare Match Register 0_1 TCMR0_1
16
H'FFFF0898
Timer Compare Match Register 1_1 TCMR1_1
16
H'FFFF089C
Timer Compare Match Register 2_1 TCMR2_1
16
H'FFFF08A0
Tx-Trigger Time Selection
Register_1
Mailbox n Control 0_H_1
(n = 0 to 31)
TTTSEL_1
16
MBn_CONTROL0_H_1 16
(n = 0 to 31)
H'FFFF08A4
H'FFFF0900
+ n×32
Mailbox n Control 0_L_1
(n = 0 to 31)
MBn_CONTROL0_L_1 16
(n = 0 to 31)
H'FFFF0902
+ n×32
Mailbox n Local Acceptance Filter MBn_LAFM0_1
Mask 0_1 (n = 0 to 31)
(n = 0 to 31)
16
H'FFFF0904
+ n×32
Mailbox n Local Acceptance Filter MBn_LAFM1_1
Mask 1_1 (n = 0 to 31)
(n = 0 to 31)
16
H'FFFF0906
+ n×32
Mailbox n Data 01_1 (n = 0 to 31) MBn_DATA_01_1
16
(n = 0 to 31)
H'FFFF0908
+ n×32
Mailbox n Data 23_1 (n = 0 to 31) MBn_DATA_23_1
16
(n = 0 to 31)
H'FFFF090A
+ n×32
Mailbox n Data 45_1 (n = 0 to 31) MBn_DATA_45_1
16
(n = 0 to 31)
H'FFFF090C
+ n×32
Mailbox n Data 67_1 (n = 0 to 31) MBn_DATA_67_1
16
(n = 0 to 31)
H'FFFF090E
+ n×32
Mailbox n Control 1_1 (n = 0 to 31) MBn_CONTROL1_1 16
(n = 0 to 31)
H'FFFF0910
+ n×32
Mailbox n Time Stamp_1
(n = 0 to 15, 30, 31)
MBn_TIMESTAMP_1 16
(n = 0 to 15, 30, 31)
H'FFFF0912
+ n×32
Mailbox n Trigger Time_1
(n = 24 to 30)
MBn_TTT_1
(n = 24 to 30)
16
H'FFFF0914
+ n×32
Mailbox n TT Control_1
(n = 24 to 29)
MBn_TTCONTROL_1 16
(n = 24 to 29)
H'FFFF0916
+ n×32
IEB
IEBus control register
IECTR
8
H'FFFEF000
IEBus command register
IECMR
8
H'FFFEF001
IEBus master control register
IEMCR
8
H'FFFEF002
Access
Size
16
16
16
16
16
16
16, 32
16
16, 32
16
8, 16, 32
8, 16
8, 16, 32
8, 16
8, 16
16
16
16
8
8
8
Rev. 2.00 Mar. 14, 2008 Page 1616 of 1824
REJ09B0290-0200