SH7263 Datasheet, PDF (1772/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 35 Electrical Characteristics
35.4.8 SCIF Timing
Table 35.13 SCIF Timing
Conditions: VCC = PLLVCC = USBDVCC = 1.1 to 1.3 V, PVCC = USBDPVCC = 3.0 to 3.6 V,
AVCC = 3.0 to 3.6 V, USBAVCC = 1.1 to 1.3 V, USBAPVCC = 3.0 to 3.6 V,
VSS = PLLVSS = PVSS = AVSS = USBDVSS = USBAVSS = USBDPVSS =
USBAPVSS = 0 V, Ta = −40 to 85 °C
Item
Symbol Min.
Max.
Input clock cycle (clocked synchronous) t
12
—
Scyc
(asynchronous)
4
—
Input clock rise time
Input clock fall time
Input clock width
Transmit data delay time
(clocked synchronous)
t_SCKr
t
SCKf
t_SCKW
t
TXD
—
—
0.4
—
1.5
1.5
0.6
3 t + 15
pcyc
Receive data setup time
(clocked synchronous)
t
4 t + 15 —
RXS
pcyc
Receive data hold time
(clocked synchronous)
t_RXH
1 t_pcyc + 15 —
Note: t_pcyc indicates the peripheral clock (Pφ) cycle.
Unit
t
pcyc
t_pcyc
t_pcyc
t
pcyc
t_Scyc
ns
ns
ns
Figure
Figure 35.51
Figure 35.51
Figure 35.51
Figure 35.51
Figure 35.51
Figure 35.52
Figure 35.52
Figure 35.52
SCK
t_SCKW
t_SCKr
t_Scyc
t_SCKf
Figure 35.51 SCK Input Clock Timing
SCK
(input/output)
TxD
(data transmit)
RxD
(data receive)
t_Scyc
t_TXD
t_RXS t_RXH
Figure 35.52 SCIF Input/Output Timing in Clocked Synchronous Mode
Rev. 2.00 Mar. 14, 2008 Page 1738 of 1824
REJ09B0290-0200