SH7263 Datasheet, PDF (307/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
Bit
Bit Name
14 to 11 TED[3:0]
Initial
Value
0000
R/W
R/W
Description
Number of Delay Cycles from Address Output to
RD/WE Assertion
Specify the number of delay cycles from address
output to RD/WE assertion for the memory card or to
ICIORD/ICIOWR assertion for the I/O card in PCMCIA
interface.
0000: 0.5 cycle
0001: 1.5 cycles
0010: 2.5 cycles
0011: 3.5 cycles
0100: 4.5 cycles
0101: 5.5 cycles
0110: 6.5 cycles
0111: 7.5 cycles
1000: 8.5 cycles
1001: 9.5 cycles
1010: 10.5 cycles
1011: 11.5 cycles
1100: 12.5 cycles
1101: 13.5 cycles
1110: 14.5 cycles
1111: 15.5 cycles
Rev. 2.00 Mar. 14, 2008 Page 273 of 1824
REJ09B0290-0200