SH7263 Datasheet, PDF (1367/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
Table 25.18 Buffer Memory Map
Buffer Memory
Number
H'0 to H'3
H'4
H'5
H'6 to H'7F
Buffer Size
256 bytes
64 bytes
64 bytes
Up to 7808
bytes
Pipe Setting Note
DCP special
fixed area
Single buffer, continuous transfers
enabled
Fixed area for Single buffer
PIPE6
Fixed area for Single buffer
PIPE7
PIPE1 to PIPE5 Double buffer can be set, continuous
user area
transfers enabled
(d) Auto Buffer Clear Mode Function
With this module, all of the received data packets are discarded if the ACLRM bit in PIPEnCTR is
set to 1. If a normal data packet has been received, the ACK response is returned to the host
controller. This function can be set only in the buffer memory reading direction.
Also, if the ACLRM bit is set to 1 and then to 0, the buffer memory of the pipe can be cleared
regardless of the access direction.
An access cycle of at least 100 ns is required between ACLRM = 1 and ACLRM = 0.
(e) Buffer Memory Specifications (Single/Double Setting)
Either a single or double buffer can be selected for PIPE1 to PIPE5, using the DBLB bit in
PIPEnCFG. The double buffer is a function that assigns two memory areas specified with the
BUFSIZE bit in PIPEBUF to the same pipe. Figure 25.10 shows an example of buffer memory
settings for this module.
Buffer memory
64 bytes
PIPEBUF registers
BUFSIZE = 0,
DBLB = 0
64 bytes
64 bytes
BUFSIZE = 0,
DBLB = 1
128 bytes
BUFSIZE = 1,
DBLB = 0
Figure 25.10 Example of Buffer Memory Settings
Rev. 2.00 Mar. 14, 2008 Page 1333 of 1824
REJ09B0290-0200