SH7263 Datasheet, PDF (943/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-TL1)
Important: Although core of RCAN-TL1 is designed based on a 32-bit bus system, the whole
RCAN-TL1 including MPI for the CPU has 16-bit bus interface to CPU. In that case, LongWord
(32-bit) access must be implemented as 2 consecutive word (16-bit) accesses. In this manual,
LongWord access means the two consecutive accesses.
• Micro Processor Interface (MPI)
The MPI allows communication between the Renesas CPU and the RCAN-TL1’s
registers/mailboxes to control the memory interface. It also contains the Wakeup Control logic
that detects the CAN bus activities and notifies the MPI and the other parts of RCAN-TL1 so
that the RCAN-TL1 can automatically exit the Sleep mode.
It contains registers such as MCR, IRR, GSR and IMR.
• Mailbox
The Mailboxes consists of RAM configured as message buffers and registers. There are 32
Mailboxes, and each mailbox has the following information.
<RAM>
⎯ CAN message control (identifier, rtr, ide, etc)
⎯ CAN message data (for CAN Data frames)
⎯ Local Acceptance Filter Mask for reception
<Registers>
⎯ CAN message control (dlc)
⎯ Time Stamp for message reception/transmission
⎯ 3-bit wide Mailbox Configuration, Disable Automatic Re-Transmission bit, Auto-
Transmission for Remote Request bit, New Message Control bit
⎯ Tx-Trigger Time
• Mailbox Control
The Mailbox Control handles the following functions.
⎯ For received messages, compare the IDs and generate appropriate RAM addresses/data to
store messages from the CAN Interface into the Mailbox and set/clear appropriate registers
accordingly.
⎯ To transmit event-triggered messages, run the internal arbitration to pick the correct
priority message, and load the message from the Mailbox into the Tx-buffer of the CAN
Interface and set/clear appropriate registers accordingly. In the case of time-triggered
transmission, compare match of Tx-Trigger time invoke loading the messages.
⎯ Arbitrates Mailbox accesses between the CPU and the Mailbox Control.
⎯ Contains registers such as TXPR, TXCR, TXACK, ABACK, RXPR, RFPR, UMSR and
MBIMR.
Rev. 2.00 Mar. 14, 2008 Page 909 of 1824
REJ09B0290-0200