SH7263 Datasheet, PDF (1121/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
Name
Initial
Abbreviation R/W Value Address
Access
Size
Post-ECC correction subheader:
SHEAD25
channel number (byte 21) data register
R H'00 H'FFFC202D 8
Post-ECC correction subheader:
sub-mode (byte 22) data register
SHEAD26 R H'00 H'FFFC202E 8
Post-ECC correction subheader:
data type (byte 23) data register
SHEAD27 R H'00 H'FFFC202F 8
Automatic buffering setting control
register
CBUFCTL0 R/W H'04 H'FFFC2040 8
Automatic buffering start sector setting: CBUFCTL1 R/W H'00 H'FFFC2041 8
minutes control register
Automatic buffering start sector setting: CBUFCTL2 R/W H'00 H'FFFC2042 8
seconds control register
Automatic buffering start sector setting: CBUFCTL3 R/W H'00 H'FFFC2043 8
frames control register
ISY interrupt source mask control
register
CROMST0M R/W H'00 H'FFFC2045 8
CD-ROM decoder reset control register ROMDECRST R/W H'00 H'FFFC2100 8
CD-ROM decoder reset status register RSTSTAT R H'00 H'FFFC2101 8
SSI data control register
SSI
R/W H'18 H'FFFC2102 8
Interrupt flag register
INTHOLD
R/W H'00 H'FFFC2108 8
Interrupt source mask control register INHINT
R/W H'00 H'FFFC2109 8
CD-ROM decoder stream data input
register
STRMDIN0 R/W H'0000 H'FFFC2200 Read: 16
Write: 16/32
CD-ROM decoder stream data input
register
STRMDIN2 R/W H'0000 H'FFFC2202 16
CD-ROM decoder stream data output STRMDOUT0 R
register
H'0000 H'FFFC2204 16, 32
Rev. 2.00 Mar. 14, 2008 Page 1087 of 1824
REJ09B0290-0200