SH7263 Datasheet, PDF (23/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

20.4.1 Transmission Format .......................................................................................... 1064
20.4.2 Reception Format................................................................................................ 1065
20.5 Software Control Flows ................................................................................................... 1066
20.5.1 Initial Setting ...................................................................................................... 1066
20.5.2 Master Transmission........................................................................................... 1067
20.5.3 Slave Reception .................................................................................................. 1068
20.5.4 Master Reception ................................................................................................ 1069
20.5.5 Slave Transmission ............................................................................................. 1070
20.6 Operation Timing............................................................................................................. 1071
20.6.1 Master Transmit Operation ................................................................................. 1071
20.6.2 Slave Receive Operation..................................................................................... 1072
20.6.3 Master Receive Operation................................................................................... 1073
20.6.4 Slave Transmit Operation ................................................................................... 1074
20.7 Interrupt Sources.............................................................................................................. 1075
20.8 Usage Notes ..................................................................................................................... 1077
20.8.1 Note on Operation when Transfer is Incomplete after Transfer
of the Maximum Number of Bytes ..................................................................... 1077
Section 21 CD-ROM Decoder (ROM-DEC)...................................................1079
21.1 Features............................................................................................................................ 1079
21.1.1 Formats Supported by ROM-DEC...................................................................... 1080
21.2 Block Diagrams ............................................................................................................... 1081
21.3 Register Descriptions ....................................................................................................... 1085
21.3.1 ROM-DEC Enable Control Register (CROMEN) .............................................. 1088
21.3.2 Sync Code-Based Synchronization Control Register (CROMSY0) ................... 1089
21.3.3 Decoding Mode Control Register (CROMCTL0) .............................................. 1090
21.3.4 EDC/ECC Check Control Register (CROMCTL1) ............................................ 1093
21.3.5 Automatic Decoding Stop Control Register (CROMCTL3)............................... 1094
21.3.6 Decoding Option Setting Control Register (CROMCTL4) ................................ 1095
21.3.7 HEAD20 to HEAD22 Representation Control Register (CROMCTL5) ............ 1097
21.3.8 Sync Code Status Register (CROMST0) ............................................................ 1098
21.3.9 Post-ECC Header Error Status Register (CROMST1)........................................ 1099
21.3.10 Post-ECC Subheader Error Status Register (CROMST3) .................................. 1100
21.3.11 Header/Subheader Validity Check Status Register (CROMST4)....................... 1101
21.3.12 Mode Determination and Link Sector Detection Status Register
(CROMST5) ....................................................................................................... 1102
21.3.13 ECC/EDC Error Status Register (CROMST6) ................................................... 1103
21.3.14 Buffer Status Register (CBUFST0) .................................................................... 1105
21.3.15 Decoding Stoppage Source Status Register (CBUFST1) ................................... 1106
21.3.16 Buffer Overflow Status Register (CBUFST2) .................................................... 1107
Rev. 2.00 Mar. 14, 2008 Page xxiii of xxxiv
REJ09B0290-0200