SH7263 Datasheet, PDF (192/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 6 Interrupt Controller (INTC)
6.4.6 On-Chip Peripheral Module Interrupts
On-chip peripheral module interrupts are generated by the following on-chip peripheral modules:
• Direct memory access controller (DMAC)
• USB2.0 host/function module (USB)
• LCD controller (LCDC)
• Compare match timer (CMT)
• Bus state controller (BSC)
• Watchdog timer (WDT)
• Multi-function timer pulse unit 2 (MTU2)
• A/D converter (ADC)
• I²C bus interface 3 (IIC3)
• Serial communications interface with FIFO (SCIF)
• Synchronous serial communications unit (SSU)
• Serial sound interface (SSI)
• CD-ROM decoder (ROM-DEC)
• AND/NAND flash memory controller (FLCTL)
• SD host interface (SDHI)
• Realtime clock (RTC)
• Controller area network (RCAN-TL1)
• Sampling rate converter (SRC)
• IEBus^TM controller (IEB)
As every source is assigned a different interrupt vector, the source does not need to be identified in
the exception service routine. A priority level in a range from 0 to 15 can be set for each module
by interrupt priority registers 05 to 17 (IPR05 to IPR17). The on-chip peripheral module interrupt
exception handling sets the I3 to I0 bits in SR to the priority level of the accepted on-chip
peripheral module interrupt.
Rev. 2.00 Mar. 14, 2008 Page 158 of 1824
REJ09B0290-0200