SH7263 Datasheet, PDF (37/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 1 Overview
Items
Floating-point unit
(FPU)
Cache memory
Interrupt controller
(INTC)
Specification
• Floating-point co-processor included
• Supports single-precision (32-bit) and double-precision (64-bit)
• Supports data type and exceptions that conforms to IEEE754 standard
• Two rounding modes: Round to nearest and round to zero
• Two denormalization modes: Flush to zero
• Floating-point registers
⎯ Sixteen 32-bit floating-point registers (single-precision × 16 words
or double-precision × 8 words)
⎯ Two 32-bit floating-point system registers
• Supports FMAC (multiplication and accumulation) instructions
• Supports FDIV (division) and FSQRT (square root) instructions
• Supports FLDI0/FLDI1 (load constant 0/1) instructions
• Instruction execution time
⎯ Latency (FAMC/FADD/FSUB/FMUL): Three cycles (single-
precision), eight cycles (double-precision)
⎯ Pitch (FAMC/FADD/FSUB/FMUL): One cycle (single-precision), six
cycles (double-precision)
Note: FMAC only supports single-precision
• Five-stage pipeline
• Instruction cache: 8 Kbytes
• Operand cache: 8 Kbytes
• 128-entries/way, 4-way set associative, 16-byte block length
configuration
• Write-back, write-through, LRU replacement algorithm
• Way-lock function available (operand cache only): ways 2 and 3 can be
locked
• Seventeen external interrupt pins (NMI, IRQ7 to IRQ0, and PINT7 to
PINT0)
• On-chip peripheral interrupts: Priority level set for each module
• 16 priority levels available
• Register bank enabling fast register saving and restoring in interrupt
processing
Rev. 2.00 Mar. 14, 2008 Page 3 of 1824
REJ09B0290-0200