SH7263 Datasheet, PDF (107/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 2 CPU
Instruction
Instruction Code
Operation
Execu-
tion
Cycles
T Bit
Compatibility
SH2,
SH2E SH4 SH-2A
EXTU.B Rm,Rn
0110nnnnmmmm1100 Byte in Rm is
zero-extended → Rn
1
⎯
Yes Yes Yes
EXTU.W Rm,Rn
0110nnnnmmmm1101 Word in Rm is
zero-extended → Rn
1
⎯
Yes Yes Yes
MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111 Signed operation of (Rn) × 4
(Rm) + MAC → MAC
32 × 32 + 64 → 64 bits
⎯
Yes Yes Yes
MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 Signed operation of (Rn) × 3
(Rm) + MAC → MAC
16 × 16 + 64 → 64 bits
⎯
Yes Yes Yes
MUL.L Rm,Rn
0000nnnnmmmm0111 Rn × Rm → MACL
32 × 32 → 32 bits
2
⎯
Yes Yes Yes
MULR R0,Rn
0100nnnn10000000 R0 × Rn → Rn
2
Yes
32 × 32 → 32 bits
MULS.W Rm,Rn
0010nnnnmmmm1111 Signed operation of Rn × Rm 1
→ MACL
16 × 16 → 32 bits
⎯
Yes Yes Yes
MULU.W Rm,Rn
0010nnnnmmmm1110 Unsigned operation of Rn × 1
Rm → MACL
16 × 16 → 32 bits
⎯
Yes Yes Yes
NEG
Rm,Rn
0110nnnnmmmm1011 0-Rm → Rn
1
⎯
Yes Yes Yes
NEGC Rm,Rn
0110nnnnmmmm1010 0-Rm-T → Rn, borrow → T 1
Borrow Yes Yes Yes
SUB
Rm,Rn
0011nnnnmmmm1000 Rn-Rm → Rn
1
⎯
Yes Yes Yes
SUBC Rm,Rn
0011nnnnmmmm1010 Rn-Rm-T → Rn, borrow → T 1
Borrow Yes Yes Yes
SUBV Rm,Rn
0011nnnnmmmm1011 Rn-Rm → Rn, underflow → T 1
Over- Yes Yes Yes
flow
Rev. 2.00 Mar. 14, 2008 Page 73 of 1824
REJ09B0290-0200