SH7263 Datasheet, PDF (473/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Direct Memory Access Controller (DMAC)
10.5.3 Notice about using external request mode
In case that one or more channels are set that transfer request source is external request signal
DREQ, please use one of the following four ways.
1) Please set all channels to cycle-steal mode.
2) Please set all channels to burst-mode with all of the following three conditions.
2-1) Please set channel priority mode to fixed mode 1 or fixed mode 2.
2-2) Please set all channels to dual-address mode.
2-3) Please set transfer source address and transfer destination address of each channels to one
of the followings.
A. transfer source address: external address space
transfer destination address: external address space
B. transfer source address: external address space
transfer destination address: internal address space
C. transfer source address: internal address space
transfer destination address: internal address space
3) If there are both of one or more channels set to cycle-steal mode and one or more channels set
to burst mode, please use with all of the following three conditions.
3-1) Please set channel priority mode to fixed mode 1 or fixed mode 2.
3-2) Please set all channels to dual-address mode.
3-3) Please set transfer source address and transfer destination address of each channels to one
of the followings.
A. transfer source address: external address space
transfer destination address: external address space
B. transfer source address: external address space
transfer destination address: internal address space
C. transfer source address: internal address space
transfer destination address: internal address space
4) Please use only one channel.
If using other than the above four ways, there is a possibility that DACKn pin and TENDn pin
show wrong transfer channel and since then until power-on reset DMA transfer is unavailable.
Additionally if this state occurs in burst-mode, CPU becomes unable to fetch instructions, then
system becomes suspended.
Rev. 2.00 Mar. 14, 2008 Page 439 of 1824
REJ09B0290-0200