SH7263 Datasheet, PDF (1276/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
1, 0
RHST[1:0] All 0
R
Reset Handshake
These bits are used to confirm the communication
speed at which communication is being carried out
with the host controller (communication bit rate).
If the high-speed operation has been disabled (the
HSE bit in SYSCFG is cleared to 0), this module
establishes the full-speed operation without
executing the reset handshake protocol. If the high-
speed operation has been enabled (the HSE bit is
set to 1), this module executes the reset handshake
protocol (RHST = 01 during the execution) and feeds
back the execution results to these bits (11 for high-
speed operation, or 10 for full-speed operation).
00: Communication speed not decided
01: Reset handshake is being handled
10: Full-speed operation established
11: High-speed operation established
Note: If RHST is not established even though
sufficient waiting time has elapsed after USB
bus reset processing was complete (after
setting USBRST = 0), the USB cable may have
been disconnected during the USB bus reset
processing. In this case, USB bus status
should be checked with the LNST bits.
Note: When the function controller function is selected, the RWUPE, USBRST, RESUME and
UACT bits must be cleared to 0.
When the host controller function is selected, the WKUP bit must be cleared to 0.
Rev. 2.00 Mar. 14, 2008 Page 1242 of 1824
REJ09B0290-0200