SH7263 Datasheet, PDF (1062/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB)
For use of active low signals, levels are reversed from the active high signals.
The synchronous and data periods have approximately the same length.
The IEBus is synchronized bit by bit. The specifications for the time of all bits and the periods
allocated to the bits differ depending on the type of transfer bits and the unit (master or slave unit).
20.1.5 Configuration
Figure 20.5 shows the entire block configuration and table 20.6 lists the functions of each block.
Transmit
data buffer
Transmit controller
Internal bus
Internal
bus
interface
Register
Receive controller
Receive
data buffer
Figure 20.5 IEB Block Diagram
IEBbus
interface
IEBus
Rev. 2.00 Mar. 14, 2008 Page 1028 of 1824
REJ09B0290-0200