SH7263 Datasheet, PDF (853/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 16 Synchronous Serial Communication Unit (SSU)
Start
[1]
Initial setting
Read SSSR
No
RDRF = 1?
Yes
ORER = 1?
Yes [2]
No
No
Consecutive data reception?
Yes
Read received data in SSRDR
RDRF automatically cleared
[1] Initial setting:
Specify the receive data format.
[2], [4] Receive error processing:
When a receive error occurs, execute the designated error
processing after reading the ORER bit in SSSR. After that,
clear the ORER bit to 0. While the ORER bit is set to 1,
reception is not resumed.
[3] To complete reception:
To complete reception, read receive data after clearing the
RE bit to 0. When reading SSRDR without clearing the RE
bit, reception is resumed.
[3]
RE = 0
Read receive data in SSRDR
End reception
[4]
Overrun error processing
Clear the ORER bit in SSSR
End reception
Note: Hatching boxes represent SSU internal operations.
Figure 16.16 Flowchart Example of Data Reception
(Clock Synchronous Communication Mode)
Rev. 2.00 Mar. 14, 2008 Page 819 of 1824
REJ09B0290-0200