SH7263 Datasheet, PDF (1292/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
9
NRDYE
0
R/W Buffer Not Ready Response Interrupts Enable
0: Interrupt output disabled
1: Interrupt output enabled
8
BRDYE
0
R/W Buffer Ready Interrupts Enable
0: Interrupt output disabled
1: Interrupt output enabled
7
URST
0
R/W Default State Transition Notifications Enable
0: DVST interrupt disabled at transition to default
state
1: DVST interrupt enabled at transition to default
state
6
SADR
0
R/W Address State Transition Notifications Enable
0: DVST interrupt disabled at transition to address
state
1: DVST interrupt enabled at transition to address
state
5
SCFG
0
R/W Configuration State Transition Notifications Enable
0: DVST interrupt disabled at transition to
configuration state
1: DVST interrupt enabled at transition to
configuration state
4
SUSP
0
R/W Suspend State Transition Notifications Enable
0: DVST interrupt disabled at transition to suspended
state
1: DVST interrupt enabled at transition to suspended
state
3
WDST
0
R/W Control Write Stage Transition Notifications Enable
0: CTRT interrupt disabled at transition to control
write stage
1: CTRT interrupt enabled at transition to control
write stage
Rev. 2.00 Mar. 14, 2008 Page 1258 of 1824
REJ09B0290-0200