SH7263 Datasheet, PDF (1154/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
Bit Bit Name
Initial
Value R/W Description
5
CBUF_LINK 0
R/W Buffering Control on Link Block Detection
0: Allocates area for seven sectors
1: Data are buffered, skipping the link block
4, 3 CBUF_MD 00
[1:0]
R/W Start-sector detection mode when the automatic
buffering function is in use
00: The header values for the previous and current
sectors must be in sequence.
01: The header value detected in the current sector
must be in sequence with the interpolated value.
10: A current sector with any header value is OK.
11: Start-sector detection is based on the interpolated
value even if the current sector is not detected.
2
CBUF_TS
1
R/W CBUFCTL1 to CBUFCTL3 Setting Mode
0: CBUFCTL1 to CBUFCTL3: BCD (in decimal)
1: Total number of sectors (in hexadecimal)
1
CBUF_Q
0
R/W Q-channel code buffering data specification in the case
of a CRC error in the Q-channel code
0: The values for the last sector for which the CRC
returned a correct result are buffered.
1: The erroneous data is buffered as is.
Note: Since subcodes are not input with this LSI,
always set this bit to 1.
0
⎯
0
R/W Reserved
This bit is always read as 0.The write value should
always be 0.
Rev. 2.00 Mar. 14, 2008 Page 1120 of 1824
REJ09B0290-0200