SH7263 Datasheet, PDF (180/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 6 Interrupt Controller (INTC)
Register Name
Interrupt priority
register 13
Interrupt priority
register 14
Interrupt priority
register 15
Interrupt priority
register 16
Interrupt priority
register 17
Bits 15 to 12
IIC3-3
SCIF3
SSI1
FLCTL
RCAN1
Bits 11 to 8
SCIF0
SSU0
SSI2
SDHI
SRC
Bits 7 to 4
SCIF1
SSU1
SSI3
RTC
IEB
Bits 3 to 0
SCIF2
SSI0
ROM-DEC
RCAN0
Reserved
As shown in table 6.3, by setting the 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3
to 0) with values from H'0 (0000) to H'F (1111), the priority of each corresponding interrupt is set.
Setting of H'0 means priority level 0 (the lowest level) and H'F means priority level 15 (the
highest level).
IPR01, IPR02, and IPR05 to IPR14 are initialized to H'0000 by a power-on reset.
Rev. 2.00 Mar. 14, 2008 Page 146 of 1824
REJ09B0290-0200