SH7263 Datasheet, PDF (1812/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Main Revisions for this Edition
Item
Page
2.1.3 System Registers 44
(3) Program Counter
(PC)
3.2.2 Non-Numbers 91
(NaN)
3.3.2 Floating-Point 95
Status/Control Register
(FPSCR)
3.5 FPU Exceptions 97
3.5.1 FPU Exception
Sources
3.5.2 FPU Exception 98
Handling
Revision (See Manual for Details)
Description amended
… PC indicates the address four bytes ahead of the instruction
being executed and controls the flow of the processing.
Description amended
PC indicates the address four bytes ahead of the instruction
being executed.
Description amended
• When the value of the EN.V bit in FPSCR is 1, FPU
exception handling is triggered by an invalid operation
exception. In this case, the contents of the operation
destination register are unchanged.
Table amended
Initial
Bit
Bit Name Value R/W Description
17 to 12 Cause
All 0
R/W FPU Exception Cause Field
11 to 7
6 to 2
Enable
Flag
All 0
All 0
R/W FPU Exception Enable Field
R/W ^{FPU Exception Flag Field}
The FPU exception source field is initially cleared to 0
when a floating-point operation instruction is executed.
When an FPU exception is generated by a floating-
point operation, the corresponding bits in the FPU
exception source field and FPU exception flag field are
set to 1. The FPU exception flag field bit remains set to
1 until it is cleared to 0 by software. FPU exception
handling occurs if the corresponding bit in the FPU
exception enable field is set to 1.
For bit allocations of each field, see table 3.3.
Title amended
Description amended
FPU exceptions may be triggered by floating point operation
instructions. The exception sources are as follows:
Description amended
The possibilities for exception handling caused by floating point
operations are described in the individual instruction
descriptions. All exception events that originate in floating point
operations are assigned as the same FPU exception handling
event. The meaning of an exception caused by a floating point
operation is determined by software by reading from FPSCR
and interpreting the information it contains. Also, the
destination register is not changed when FPU exception
handling occurs.
Except for the above, the bit corresponding to source V, Z, O,
U, or I is set to 1, and a default value is generated as the
operation result.
Rev. 2.00 Mar. 14, 2008 Page 1778 of 1824
REJ09B0290-0200