SH7263 Datasheet, PDF (875/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 17 I²C Bus Interface 3 (IIC3)
17.3.6 Slave Address Register (SAR)
SAR is an 8-bit readable/writable register that selects the communications format and sets the
slave address. In slave mode with the I²C bus format, if the upper seven bits of SAR match the
upper seven bits of the first frame received after a start condition, this module operates as the slave
device.
Bit: 7
Initial value: 0
R/W: R/W
6
0
R/W
5
4
3
SVA[6:0]
0
0
0
R/W R/W R/W
2
0
R/W
1
0
R/W
0
FS
0
R/W
Bit
7 to 1
Bit Name
SVA[6:0]
0
FS
Initial
Value R/W
0000000 R/W
0
R/W
Description
Slave Address
These bits set a unique address in these bits,
differing form the addresses of other slave devices
connected to the I²C bus.
Format Select
0: I²C bus format is selected
1: Clocked synchronous serial format is selected
17.3.7 I²C Bus Transmit Data Register (ICDRT)
ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the
space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to
ICDRS and starts transferring data. If the next transfer data is written to ICDRT while transferring
data of ICDRS, continuous transfer is possible.
Bit: 7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 2.00 Mar. 14, 2008 Page 841 of 1824
REJ09B0290-0200